Home > Events > Oral Candidacy - Indranil Palit

Oral Candidacy - Indranil Palit

Start: 8/5/2014 at 9:00AM
End: 8/5/2014 at 1:00PM
Location: 315 Stinson Remick
Add to calendar:
iCal vCal

Indranil Palit

Oral Candidacy Exam, August 5th, 9:00 am, 315 Stinson Remick

Advisor:  Dr. Sharon Hu               Co-Advisor:  Dr. Michael Niemier

Committee Members:

Dr. Gyorgy Csaba       Dr. Joseph Nahas        Dr. Wolfgang Porod



It is well known that CMOS scaling trends are now accompanied by less desirable byproducts such as increased energy dissipation. To combat the aforementioned challenges, solutions are sought at both the device and architectural levels. With this context, this proposal focuses on developing a systematic circuit design methodology for Nanomagnet Logic (NML) devices, and exploring the benefits of utilizing beyond-CMOS emerging transistors to process information with the non-binary/non-von Neumann computer architecture of Cellular Neural Networks (CNNs). Nanomagnet Logic (NML) is an emerging device architecture that performs logic operations through fringing field interactions between nano-scale magnets. The design space for NML circuits is large and so far there exists no systematic approach for determining the parameter values (e.g., device-to-device spacings, clocking field strength etc.) to generate a predictable design solution. This work presents a formal methodology for designing NML circuits that marshals the design parameters to generate a layout that is guaranteed to evolve correctly in time at 0K. The approach is further augmented to identify functional design targets when considering thermal noise associated with higher temperatures. A Cellular Neural Network (CNN) is a highly-parallel, analog processor that can significantly outperform von Neumann architectures for certain classes of problems. This proposal shows that emerging technologies like tunneling field effect transistors (TFETs) can be successfully employed in CNNs to solve binary classification problems. Such systems provide significant power savings when compared to the conventional resistor-based CNN. Moreover, TFET-based CNN reduces implementation footprints by eliminating the hardware required to realize output transfer functions. It is also shown how emerging, beyond-CMOS devices could help to further enhance the capabilities of CNNs, particularly for solving problems with non-binary outputs. CNNs based on devices such as graphene transistors -- with multiple steep current growth regions separated by negative differential resistance (NDR) in their I-V characteristics -- could be used to recognize multiple patterns simultaneously, (This would require multiple steps given a conventional, binary CNN.) Also, a circuit built from TFETs is used in CNN to perform similar tasks. With this approach, more "exotic" device I-V characteristics are not required -- which should be an asset when considering issues such as cell-to-cell mismatch, etc. As a case study, a CNN-cell design is presented that employs TFET-based circuitry to realize ternary outputs, and employed to efficiently solve a tactile sensing problem. The total number of computation steps as well as the required hardware could be reduced significantly when compared to an approach based on a conventional CNN. To complement the existing works, future plans are proposed with the goal of improving both the energy dissipation, and functionalities of CNN systems.

« March 2017 »