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Oral Candidacy - Robert Perricone

Start: 5/16/2016 at 1:00PM
End: 5/16/2016 at 3:00PM
Location: 257G Fitzpatrick Hall
Attendees: Faculty and students are welcome to attend the presentation portion of the defense.
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Oral Candidacy

Robert Perricone

May 16, 2016          1:00 pm          257G Fitzpatrick

Advisers:  Dr. Sharon Hu and Dr. Michael Niemier

Committee Members:

Dr. Peter Kogge        Dr. Joseph Nahas        Dr. Yiyu Shi



Towards Computing in the Beyond-CMOS Era: A Study of Beyond-CMOS Circuits and Architectures


As we continue to approach the physical scaling limits of CMOS transistors, microprocessors no longer achieve exponential performance gains per each technology node generation.  This performance attenuation is attributed to the diminishing rate of supply voltage scaling and the increasing sub-threshold leakage current.  These have resulted in a growing---as opposed to constant---power density, which has given birth to the dark silicon (DS) problem.  To overcome DS, solutions are sought from the device to the architectural level.  

Beyond-CMOS devices represent a class of candidate technologies with the potential to succeed traditional CMOS.  As new electronic and spintronic devices are continually developed and refined, benchmarking against CMOS becomes an necessary endeavor.  In this context, my work has involved the design and evaluation of circuits and architectures comprised of emerging electronic and spintronic devices.  To this end, I have constructed an analytical benchmarking model---from the device to the architectural/application level---that evaluates CMOS and electronic beyond-CMOS devices.  However, unlike electronic devices, spintronic devices do not have well-established logic and memory circuits---the building blocks of a computational architecture.  For spintronic devices, my work has involved the systematic design of functional 3D Nanomagnetic Logic (NML) layouts (i.e., logic gates) in addition to exploring the benefits of NML-based Stochastic Computing (SC).

NML uses bistable magnets to store, process, and move binary information through magnetic field-coupled interactions.  Compared to CMOS, NML has several advantages such as non-volatility, lower power consumption, and radiation hardness.  3D NML layouts provide additional benefits such as simplified signal routing and greater integration density.  The current process of designing 3D NML layouts is little more than a trial-and-error-based approach, which is infeasible for larger, more complex designs.  To address this design limitation, I developed a systematic approach that leverages a machine learning-inspired prediction methodology to enable faster design of functional 3D NML layouts.

The systematic design approach facilitated the study of more complex computational paradigms such as SC.  SC offers low-cost implementations of arithmetic operations and high degrees of error tolerance.  Given that spintronic devices such as NML are more prone to error than electronic devices, the marriage of SC and spin-based devices has the potential to produce information processing systems that are robust, low energy and non-volatile.  I introduced and evaluated new NML layouts that exploited unique features of the technology to efficiently realize hardware components required for SC.

Finally, to complement my existing work, I propose more comprehensive investigations on the impacts of beyond-CMOS devices at the architectural level.  I will evaluate the performance/power tradeoffs of electronic beyond-CMOS devices in the context of cache memory and on-chip accelerators.  To conclude, I will bring my work full circle by investigating and evaluating spintronic devices at the architecture/application level.


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