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PhD Defense - Indranil Palit

Start: 11/15/2016 at 12:15PM
End: 11/15/2016 at 3:30PM
Location: 315 Stinson Remick
Attendees: Faculty and students are welcome to the presentation portion of the defense. Light refreshments will be served.
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Indranil Palit

Doctoral Defense

            November 15, 2016      

           315 Stinson Remick         

12:15 pm 

            Adviser:  Dr. Sharon Hu           

Co-Adviser:  Dr. Micheal Niemier

Committee Members:

Dr. Suman Datta        Dr. Joseph Nahas        Dr. Yiyu Shi




It is well known that CMOS scaling trends are now accompanied by less desirable byproducts such as increased energy dissipation. To combat the aforementioned challenges, solutions are sought at both the device and architectural levels. With this context, this work focuses on developing a systematic circuit design methodology for Nanomagnet Logic (NML) devices, and exploring the benefits of utilizing beyond-CMOS emerging transistors to process information with the non-binary/non-von Neumann computer architecture of Cellular Neural Networks (CNNs).

Nanomagnet Logic (NML) is a device architecture that performs logic operations through fringing field interactions between nano-scale magnets. The design space for NML circuits is large and so far there exists no systematic approach for determining the parameter values (e.g., device-to-device spacings, clocking field strength etc.) to generate a predictable design solution. This work presents a formal methodology for designing NML circuits that marshals the design parameters to generate a layout that is guaranteed to evolve correctly in time at 0K. The approach is further augmented to identify functional design targets when considering thermal noise associated with higher temperatures.

A Cellular Neural Network (CNN) is a highly-parallel, analog processor that can significantly outperform von Neumann architectures for certain classes of problems. This work shows that emerging technologies like tunneling field effect transistors (TFETs) can be successfully employed in CNNs to solve binary classification problems. Such systems provide significant power, and area savings when compared to the conventional resistor-based CNN. It is also shown how emerging, beyond-CMOS devices could help to further enhance the capabilities of CNNs, particularly for solving problems with non-binary outputs. CNNs based on devices such as TFETs, graphene transistors could be used to recognize multiple patterns simultaneously, (This would require multiple steps given a conventional, binary CNN.) As a case study, a CNN-cell design is presented that employs TFET-based circuitry to realize ternary outputs, and employed to efficiently solve a tactile sensing problem. The total number of computation steps as well as the required hardware could be reduced significantly when compared to an approach based on a conventional CNN. Much existing work reports energy dissipation for CNNs at the chip level, which includes dissipation of sensors, actuators, and other components. As such, the impacts of various system variables, e.g., application templates, characteristics of the resistive element, etc., on the energy profile of a CNN cannot be easily determined. This work also proposes analytical models to estimate CNN power and performance. Simulation results show that the proposed models predict power dissipation and settling time with less than 1% and 3% errors, respectively. This work also studies the potential of analog/mixed-signal information processing using TFETs in the context of cellular neural networks (CNNs). A TFET-based, mixed signal CNN architecture for spatio-temporal information processing is presented that is projected to be at least 2x power efficient for a number of different CNN templates, when compared to state-of-the-art hardware assuming CMOS technology.

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