Cadence

Advanced Microprocessor Design Software

University of Notre Dame
Cadence University Program Member

The Cadence tool suite is a critical part of both the education and research program in the Department of Computer Science and Engineering and the Department of Electrical Engineering at the University of Notre Dame.

Education

Starting in the 2007-08 academic year, the CSE 40462/60462: VLSI Design course switched over to a Cadence-based flow for student design projects. The course has an enrollment of approximately 25 students with a mix of computer engineering and electrical engineering seniors and graduate students. A complete description of the course is located at http://www.cse.nd.edu/courses/cse60462/www/. In the course, we do a combination of custom and standard cell-based layout and design using Virtoso and Encounter. For our flow, we use the NCSU design kit (http://www.eda.ncsu.edu/wiki/NCSU_CDK) together with the Oklahoma State University cell libraries and scripts (http://avatar.ecen.okstate.edu/projects/scells/).

Student projects for the fall 2007 semester included:

  • an FIR filter
  • a successive-approximation A/D converter
  • a low-power SRAM
  • an 8-bit MIPS microprocessor, based on a Verilog implementation in Weste and Harris "CMOS VLSI Design"


Student projects for the fall 2008 semester included:

  • a 32-Bit Mersenne Twister Random Number Generator ASIC
  • an AES Encryptor
  • an Audio Playback IC (several versions)
  • an Output Driver for Quilt Packaging
  • a Dual-Rail Multiplier Using Asynchronous Logic Element
  • a Successive Approximation A/D Converter


Student projects for the fall 2009 semester included:

  • Modeling Inductive Coupling Interconnect
  • Sigma-Delta A/D Converter
  • IC Music Chip
  • NML-MTJ Interface Sensing
  • Intel 4004 Emulator
  • Boolean Satiability Problem
  • Successive Approximation A/D Converter


Student projects for the fall 2010 semester included:

  • Bandgap Reference
  • RCA 1802
  • BoronNitride FET Spice model and circuit
  • Nintendo Entertainment System (MOS-6502 plus Picture Processing Unit)
  • Tunne-Diode SRAM Sense Amplifier
  • CMOS input circuit (field based) for NML
  • A SIMD architecture processor


Student projects for the fall 2011 semester included:

  • Analog designs using analog simulation and manual layout:
    • CMOS constant voltage source at low supply voltage
    • Switch Capacitor Converter
    • Successive Approximation Analog-to-Digital Converter
    • Speaker Crossover Circuit
    • MoS2 based Transistor Model and Logic Circuit
  • Digital designs using verilog simulation and automatic place and route:
    • Intel 4004 Microprocessor
    • Sorting, RCA1802-style
    • RCA 1802 Microprocessor
    • Snake Game on FPGA
    • 6502 Microprocessor

Usage in the Fall 2013 semester was not as a final project like other years, but topics covered included:

  • Analog capture and layout of basic CMOS cells, transistors, logic gates, and ring oscillators using Virtuoso
    • Study the effects of fanout and capacitances in the layouts
  • Design rule checks (DRC) and layout vs. schematic (LVS) validation
  • Behavioral and structural Verilog design entry and simulation using NCVerilog / SimVision
    • Complex gates, counters, memory modules
  • Logic synthesis of small student designs using Encounter RTL:
    • XOR gate
    • Parity generator
    • Gray code and standard binary counters
  • Place-and-route using Encounter RTL-to-GDSII System
    • Small student designs
    • MIPS microprocessor example

Research

Notre Dame has an active research program in micro- and nanoelectronics (http://www.nd.edu/~ndnano/). In spring 2008, Notre Dame was named as the home for the Semiconductor Research Corporation (SRC) Midwest center for nanoelectronics (http://newsinfo.nd.edu/content.cfm?topicid=27158).

In Spring 2010 one of our faculty used Cadence tools in some MRAM design studies. In fall 2010 two of our faculty intend to use Cadence tools as part of preproposal studies for a NASA grant proposal.

From fall 2011 to summer 2012, we started using the Cadence Analog Design Environment for NML (Nanomagnetic Logic) Research. Fall 2012 through summer 2013 we are continuing this research.

Page last updated 6/26/2014 by


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