Davide Bertozzi - Network-on-Chip-Enabled Flexible Partitioning and Isolation of Multi-Workload-Homogeneous Manycores
With tens or even hundreds of compute cores on a single processor, many-core platforms provide enough computational performance to host several applications, while their low energy consumption makes them well-suited to serve as programmable accelerators in the high-performance embedded computing domain. The consolidation of several types of applications with different criticality levels on the same hardware platform raises severe practical issues, ranging from system composability challenges for easier verification to performance predictability and security concerns. Space partitioning is an intuitive way of meeting the above requirements. Unfortunately, it can be supported only as an afterthought in current many-core accelerators, thus leading to poor control over interferences and/or sub-optimal performance. This talk presents a systematic approach to flexible partitioning and isolation in array fabrics of homogeneous processing cores, which has its key enabler in the on-chip interconnection network. By combining reconfigurable hardware extensions in the packet routing mechanism with network-level design methods, the talk lays the foundation of a “design-for-partitioning” philosophy that can bring the usage model of many-core accelerators into new ground. As an example, it becomes possible to enforce low-power operation of multi-workload embedded systems by augmenting partitioning with adaptivity, thus yielding to dynamic hardware platforms for future automotive, avionics, high-end multimedia or smart city applications. Last but not least, the talk will review evolutionary as well as revolutionary interconnect technologies in light of their capability to fulfil the above resource sharing requirements.
Davide Bertozzi got his PhD in Electrical Engineering and Computer Science from University of Bologna in 2003. Since 2004 he holds an Assistant Professor position at University of Ferrara, where he is the principal investigator of the MPSoC Research Group (http://mpsoc.unife.it/~mpsocgroup/). He has been visiting researcher at international academic institutions (Stanford University) and large semiconductor companies (NEC America Labs, NXP Semiconductors, STMicroelectronics, Samsung Electronics). By building on his core expertise on all aspects of on-chip communication, his current research interests span from interconnect-centric heterogeneous parallel computing architectures to design automation for emerging interconnect technologies. He has been involved either as technical leader or principal investigator in research initiatives funded by the European Union (FP7 Galaxy, NaNoC and vIrtical projects) and by the Italian Government (national program for young talented researchers “FIRB 2008”). He is a member of the Hipeac Network-of-Excellence. He has published more than 150 scientific contributions, including conference proceedings, journal papers and book chapters, and has co-edited a book on networks-on-chip for CRC Press in 2010. He received four best paper awards (NOCS 2016, NOCS 2010, MCSoC 2012, SAMOS 2012), three best paper award nominations (DAC 2006, DATE 2013, ASYNC 2015), and a high-impact paper award for one of the most-cited papers ever submitted to ICCD in 30 years.