Home > Seminars > Vivek De - Energy Efficient Computing in Nanoscale CMOS

Vivek De - Energy Efficient Computing in Nanoscale CMOS


10/12/2017 at 3:30PM


10/12/2017 at 4:45PM


140 DeBartolo


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Xiaobo Hu

Xiaobo Hu

VIEW FULL PROFILE Email: shu@nd.edu
Phone: 574-631-6015
Website: http://www.nd.edu/~shu/
Office: 323A Cushing
Dr. Hu's research spans several areas including hardware-software codesign, real-time embedded systems, low-power system design, and computer-aided treatment planning. An underlying characteristic common to these topics is the employment of algorithm design and analysis techniques to solve ...
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Future computing systems spanning exascale supercomputers to wearable devices demand orders of magnitude improvements in energy efficiency while providing desired performance. The system-on-chip (SoC) designs need to span a wide range of performance and power across diverse platforms and workloads. The designs must achieve robust near-threshold-voltage (NTV) operation in nanoscale CMOS  process while supporting a wide voltage-frequency operating range with  minimal impact on die cost. We will discuss circuit and design technologies to overcome the challenges posed by device parameter variations, supply noises, temperature excursions, aging-induced degradations, workload and activity changes, and reliability considerations. The major pillars of energy-efficient SoC designs are: (1) circuit/design optimizations for fine-grain multi-voltage & wide dynamic range, (2) fine-grain on-die power delivery & management, (3) dynamic adaptation & reconfiguration, (4) dynamic on-die error detection & correction, and (5) efficient interconnects.

Seminar Speaker:

Vivek De

Vivek De


Vivek De is an Intel Fellow and Director of Circuit Technology Research in Intel Labs. He is responsible for providing strategic technical directions for long term research in future circuit technologies and leading energy efficiency research across the hardware stack. He has 262 publications in refereed international conferences and journals with a citation H-index of 67, and 216 patents issued with 26 more patents filed (pending). He received an Intel Achievement Award for his contributions to an integrated voltage regulator technology. He received a Best Paper Award at the 1996 IEEE International ASIC Conference, and nominations for Best Paper Awards at the 2007 IEEE/ACM Design Automation Conference (DAC) and 2008 IEEE/ACM International Conference on Computer-Aided Design (ICCAD). One of his publications was recognized in the 2013 IEEE/ACM Design Automation Conference (DAC) as one of the "Top 10 Cited Papers in 50 Years of DAC". Another one of his publications received the “Most Frequently Cited Paper Award” in the IEEE Symposium on VLSI Circuits at its 30th Anniversary in 2017. He was recognized as a Prolific Contributor to the IEEE International Solid-State Circuits Conference (ISSCC) at its 60th Anniversary in 2013, and a Top 10 Contributor to the IEEE Symposium on VLSI Circuits at its 30th Anniversary in 2017 . He served as an IEEE/EDS Distinguished Lecturer in 2011 and an IEEE/SSCS Distinguished Lecturer in 2017-18. He received the 2017 Distinguished Alumnus Award from the Indian Institute of Technology (IIT) Madras. He received a B.Tech from IIT Madras, India, a MS from Duke University, Durham, North Carolina, and a PhD from Rensselaer Polytechnic Institute, Troy, New York, all in Electrical Engineering. He is a Fellow of the IEEE.