Home > Seminars > Yu Wang - Neural Network on ReRAM

Yu Wang - Neural Network on ReRAM

Start:

8/25/2016 at 3:30PM

End:

8/25/2016 at 5:00PM

Location:

356A Fitzpatrick

Host:

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Xiaobo Hu

Xiaobo Hu

VIEW FULL PROFILE Email: shu@nd.edu
Phone: 574-631-6015
Website: http://www.nd.edu/~shu/
Office: 323A Cushing
Dr. Hu's research spans several areas including hardware-software codesign, real-time embedded systems, low-power system design, and computer-aided treatment planning. An underlying characteristic common to these topics is the employment of algorithm design and analysis techniques to solve ...
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574-631-6015
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The world is experiencing a data revolution to discover knowledge in big data. Large scale neural networks are one of the mainstream tools of big data analytics. However, these methods causes much more energy for computation and memory than traditional computer vision algorithms. An energy efficient method to implement large-scale neural networks is highly demanded. RRAM (or memristor) and its crossbar structure provide a promising solution to perform the computation in memory and can significantly boost the energy/power efficiency of big data applications like neuromorphic computation and Deep Learning. I will introduce energy efficient implementation of neural networks by taking advantage of the emerging RRAM technique. The main challenges and possible solutions of RRAM-based system design will be discussed in details. I will also present some recent results on different kinds of energy efficient NNs based on RRAM, such as CNN, SNN, DNN and etc. Some recent progress on chip design and planning to verify the above designs of RRAM-based neural networks will also be introduced.

Seminar Speaker:

Yu Wang

Tsinghua University

Yu Wang received his B.S. degree in 2002 and Ph.D. degree (with honor) in 2007 from Tsinghua University, Beijing. He is currently a Tenured Associate Professor with the Department of Electronic Engineering, Tsinghua University.

His research interests include brain inspired computing, application specific hardware computing, parallel circuit analysis, and power/reliability aware system design methodology. Dr. Wang has authored and coauthored over 130 papers in refereed journals and conferences. He has received Best Paper Award in ISVLSI 2012 and Best Poster Award in HEART 2012 with 6 Best Paper Nominations. He is a recipient of IBM X10 Faculty Award in 2010. He served as TPC chair for ICFPT 2011 and Finance Chair of ISLPED 2012-2016, and served as program committee member for leading conferences in these areas, including top EDA conferences such as DAC, DATE, ICCAD, ASP-DAC, and top FPGA conferences such as FPGA and FPT. Currently he serves as Associate Editor for IEEE Transactions on CAD and Journal of Circuits, Systems, and Computers. He also serves as guest editor for Integration, the VLSI Journal and IEEE Transactions on Multi-Scale Computing Systems.