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Oral Candidacy - Xunzhao Yin

Start: 5/18/2017 at 2:00PM
End: 5/18/2017 at 5:00PM
Location: 257G Fitzpatrick
Attendees: Faculty and students are welcome to attend the presentation portion of the proposal defense.
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Xunzhao Yin

Oral Candidacy

May 18, 2017          2:00pm          257G Fitzpatrick

Adviser:  Dr. Sharon Hu and Dr. Michael Niemier


Dr. Suman Datta        Dr. Zoltan Toroczkai       Dr. Yiyu Shi


In recent years the end of Dennard scaling and Dark Silicon problem are challenging both the existing technologies and Von Neumann architectures. On the one hand, the increasing subthreshold leakage current of CMOS as the device size reduces to sub-$\mu$m scale becomes a major concern in integrated circuit (IC) designs, resulting in  significant power consumption; on the other hand, in the era of "Internet of Thing" (IoT) and "Big Data", many computational needs of interest are more data-centric than compute-centric, and the redundant data processing tasks, associated with traditional Von Neumann architectures have led to  energy and performance inefficient processing and energy consuming bottleneck in moving/acquiring data from memory to processing units.

Both industry and academia are looking for the solutions to above challenges by harnessing  innovations from device to architecture level. New devices based on different materials, switching mechanisms and device structures have been explored to search for an ultimate CMOS replacement, or complemented candidates that enable equivalent scaling or improvements in beyond-CMOS fabrics for specific applications in terms of performance, energy, area, security, etc.Another class of emerging devices exhibit I-V characteristic dissimilar to that of CMOS, and they have shown the potential in gaining more benefits than CMOS in information processing systems and non-traditional computing applications such as logic-in-memory (LiM) functions.

Non-Von Neumann architectures, such as neuro-inspired, memory based computing, non-volatile processor and application-specific integrated circuits (ASICs) etc. are intensively developed to enhance the performance and energy efficiency across a wide variety of application spaces such as imaging processing, recognition and natural language processing, energy harvesting systems and optimization problems. Moreover, most of these architectures provide enhancements in performance and energy efficiency and align well with emerging beyond-CMOS devices as well. Therefore the research efforts mentioned above together are promising to provide fundamentally and holistic perspective to address the issues and challenges faced by our current computing infrastructure.

With the collaboration and support from both device and theory sides, we are able to laid our research interest in developing fundamental hardware solutions to improve the area, energy and performance, etc. efficiency or essential properties of various embedded systems from mobile devices to data centers. We have worked on designing circuits and systems that are essential to future computational platforms and applications based on the devices that have unique I-V characteristics such as bell-shaped curve or hysteresis. We have also co-optimized efficient analog hardware and enabled silicon-based technology as a template for the next generation of computing, especially for the optimization, or satisfiability problems.