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PhD Defense - Yue Ma

Start: 11/9/2018 at 8:30AM
End: 11/9/2018 at 11:30AM
Location: 165 Fitzpatrick
Attendees: Faculty and students are welcome to attend the presentation portion of the defense.
Light refreshments will be served.
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Yue Ma

PhD Defense

November 9, 2018    8:30 am   165 Fitzpatrick

Adviser:  Dr. Sharon Hu

Committee Members:

Dr. Robert Dick     Dr. Michael Niemier      Dr. Yiyu Shi

         Title:

             “Improving Reliability of Real-Time Embedded Systems”

        Abstract:

Multi-processing system-on-chips (MPSoCs) provide high performance and power efficiency. They have been widely used in many real-time applications such as automotive electronics, industrial automation, and avionics. Most of these applications must satisfy explicit deterministic or probabilistic timing constraints.

However, due to CMOS technology scaling, multicore chips increasingly have higher power density and temperature, which, in turn, weakens the reliability and reduces system lifetime. Meanwhile, the decreased feature size of transistors and low core voltage and frequency design make the circuit more vulnerable to transient faults and degrade soft-error reliability. A systematic research to maintain the quality of service, improve lifetime reliability and soft-error reliability, and satisfy the real-time requirement becomes a major design concern in current computer systems, especially for embedded systems deployed in harsh environments.

We focus on MPSoCs with homogeneous and/or heterogeneous CPU cores, and/or integrated with GPU. We first develop an on-line framework to maximize lifetime reliability for MPSoCs through reliability-aware utilization control. Then, considering that the soft error is transient, we present a dynamic recovery allocation technique that if the remaining slack is adequate, any failed task can be recovered by executing again. Based on this technique, we propose two scheduling algorithms for task sets with different characteristics to improve system-level soft-error reliability. We focus on the ``big--little'' type MPSoCs in the third work. We introduce an on-line heuristic to maximize soft-error reliability under the peak temperature, power consumption, lifetime reliability, and real-time constraints. MPSoCs consisting of integrated CPU and GPU are desirable platforms for real-time embedded applications requiring massively parallel processing capability. Hence, in the last work, we aim at improving soft-error reliability for both CPU and GPU while satisfying the peak temperature, lifetime reliability, and real-time constraints. We have evaluated all our works on both Nvidia's TK1 and/or TX2 chip with tasks from multiple benchmark suites. The experimental results show that our works can improve lifetime reliability and/or soft-error reliability and satisfy the real-time constraint.