As we move toward increasingly general and capable AI systems, efficiency is becoming as important as intelligence itself: One must achieve greater reasoning and learning capabilities under practical constraints of computation, memory, energy, latency, and cost.
In this talk, I will discuss our recent research toward Efficient General Intelligence (EGI) from two complementary directions.
Jason Cong,
UCLA
First, I will present new approaches to AI model innovation that aim to achieve greater intelligence with fewer computational resources, such as a new hierarchical memory transformer that leverages long-term memory to substantially improve the efficiency of long-context inference, as well as application-specific small models customized through agentic reinforcement learning that can match or even outperform frontier large language models (LLMs) on targeted tasks. Second, I will discuss our work on efficient heterogeneous AI inference, including lookup-table (LUT)-based LLMs with efficient hardware acceleration, heterogeneous inference with GPU–FPGA co-design for speculative decoding, and fine-grained disaggregated inference architectures.
Together, these efforts point to a broader principle: efficiency should be viewed not merely as an implementation constraint, but as a fundamental dimension of intelligence. Achieving Efficient General Intelligence will require innovations across the AI stack—from models and algorithms to heterogeneous computing architectures—so that we can deliver increasingly capable AI with dramatically greater efficiency, scalability, and accessibility.
Jason Cong is the Volgenau Chair for Engineering Excellence Professor at the UCLA Computer Science Department (and a former department chair), with joint appointment from the Electrical and Computer Engineering Department. He is the director of Center for Domain-Specific Computing (CDSC) and the director of VLSI Architecture, Synthesis, and Technology (VAST) Laboratory. Dr. Cong’s research interests include novel architectures and compilation for customizable computing, synthesis of VLSI circuits and systems, and quantum computing. He has over 600 publications in these areas, including 20 best paper awards, and 6 papers in the FPGA and Reconfigurable Computing Hall of Fame. He and his former students co-founded AutoESL, which developed the most widely used high-level synthesis tool for FPGAs (renamed to Vivado HLS and Vitis HLS after Xilinx’s acquisition). He is member of the National Academy of Engineering, the American Academy of Arts and Sciences, and a Fellow of ACM, IEEE, and the National Academy of Inventors. He is recipient of the the IEEE Robert N. Noyce Medal “for fundamental contributions to electronic design automation and FPGA design methods” in 2022, the Phil Kaufman Award, the highest recognition in EDA, in 2024, and the ACM Chuck Thacker Breakthrough Award in 2025 “for fundamental contributions to the design and automation of field-programmable systems and customizable computing.”