Today’s chips have reached a truly astronomical scale, with some boasting more components than there are stars in the Milky Way or neurons in the human brain. Designing with such extreme complexity on a chip the size of a fingernail remains feasible, thanks to successful Electronic Design Automation tools. In this presentation, we will explore the methodologies and algorithms that enable design at an ever-increasing scale, and discuss the challenges that remain open.
IC design is a process that consists of hundreds of algorithmic steps, gradually transforming a functional description into the layout of an operational circuit. The appropriate placement and interconnection of billions of components on the IC is crucial for controlling cost, performance, reliability, and power consumption. We will delve into how these conflicting objectives are optimally managed and demonstrate how this approach meets the extreme computing requirements of Machine Learning.
Patrick Groeneveld is a lecturer in the Department of Electrical Engineering at Stanford University. He has a long career in Electronic Design Automation, working at both Cadence and Synopsys. He was Chief Technologist at Magma Design Automation where he was part of the team that developed a groundbreaking RTL-to-GDS2 synthesis product. Patrick also worked at AI hardware startups and was a Full Professor of Electrical Engineering at Eindhoven University. He serves as finance chair in the Executive Committee of the Design Automation Conference. Patrick received his M.Sc. and Ph.D. degrees from Delft University of Technology in the Netherlands.